Performance of MPICH-Madeleine

Runtime

LaBRI, INRIA Bordeaux - Sud-Ouest

High Performance Runtime Systems for Parallel Architectures

Hardware configuration:

  • Processors: Dual Intel Xeon 2.66 GHz SMT with 1 GB of RAM and 512 KB of cache
  • SCI: D337 NICs
  • Myrinet: Myrinet 2000 NICs

Point-to-Point Performance

So far, we conducted experiments on these different homogeneous protocols: Shmem, TCP over Gigabit-Ethernet, MX/GM/BIP over Myrinet and SISCI over SCI.
  • SHARED MEMORY: Comparisons between MPICH-Madeleine, MPICH-SHMEM, MPICH-P4 w/Shmem, SCI-MPICH and MPICH-GM
    Latency Bandwidth
  • GigaBit Ethernet Network: Comparisons between MPICH-Madeleine and MPICH-P4
    Latency Bandwidth
  • SCI Network: Comparisons between MPICH-Madeleine and SCI-MPICH
    Latency Bandwidth
  • Myrinet Network: Comparisons between MPICH-Madeleine (both GM and MX) and MPICH-GM
    Latency Bandwidth

HPL Performance

  • 2-Nodes Configuration: Comparisons between MPICH-Madeleine, MPICH-P4, SCI-MPICH and MPICH-GM
    With SMT (4 processes/node) Without SMT (2 processes/node)
  • 4-Nodes Configuration: Comparisons between MPICH-Madeleine, MPICH-P4, and MPICH-GM
    With SMT (4 processes/node)